Integrated circuits are connectable to “the outside world” through input nodes, output nodes, or input/output nodes such as bond pads, input pads, input/output pins, die terminals, die pads, contact pads, and so forth. Buffer circuitry, often configured as an inverter or a plurality of inverters, is interposed between such nodes and active circuitry of the integrated circuit. The buffer circuitry typically includes transistors which should be protected from over-limit electrical conditions, for example, voltages and/or currents caused by electrostatic discharge (ESD) during handling, testing and operation of the integrated circuit. Subjecting a device to ESD is referred to as an ESD event. An ESD event is an example of an over-limit electrical condition that may cause damage to the circuitry of the integrated circuit unless adequately protected. Typically, an ESD protection circuit is associated with one of the above-mentioned nodes.
Typical ESD protection circuits include circuitry that provides a low-impedance conductive path to a reference voltage such as ground and/or to a voltage supply such as VCC, to dissipate (e.g., shunt) the voltage and/or current associated with the ESD event before operational circuitry of the integrated circuit is damaged. As an example of a conventional protection circuit for an output circuit with a pull-up and a pull-down transistor forming an inverter, a diode may be coupled in parallel with the pull-up transistor, a diode may be coupled in parallel with the pull-down transistor, and an ESD clamp may be coupled between VCC and ground. In this case, for example, should an large positive voltage (with respect to a reference voltage, such as ground) from an ESD event be provided to the output node, the transient ESD current may flow up through the diode coupled in parallel with the pull-up transistor, and through the ESD clamp to ground. The transient ESD current may also flow from the output node to ground directly through the pull-down transistor of the driver circuit. A transient ESD current associated with a large negative voltage (with respect to a reference voltage, such as ground) may similarly be dissipated′.
Although some transistors may be capable of shunting some transient ESD current without damaging circuit components, other transistors may be damaged as a result of any ESD current at all. For example, high-speed input or output circuits (or other specialized circuit components) may tolerate little to no transient ESD current. In other words, some circuits may not be self-protecting. Also, as semiconductor devices continue to shrink, they become more prone to and less tolerant of ESD events. And, even if the transistors or other circuit components can tolerate a small level of transient ESD current and/or voltage, the triggering voltage of the diode or other protection circuit element may be higher than the breakdown voltage of, for example, the transistors. In this case, dedicated ESD circuits may be added, in addition to diodes, in order to help clamp the ESD voltage and/or current levels below the breakdown voltage or breakdown current of the transistors.
Some dedicated ESD circuits include circuit components that exhibit a “snap-back” characteristic. Generally, a snap-back characteristic provides a trigger condition which when exceeded, causes the circuit to enter a low-impedance state. The low-impedance state is maintained while the electrical condition on a node exceeds a hold condition. Examples of conventional circuits having snapback characteristics include thyristors, such as silicon-controlled rectifiers (SCRs), and overdriven metal-oxide-semiconductor (MOS) transistors.
In designing an adequate protection circuit using a snapback circuit, the trigger condition must be sufficiently low to provide protection before a breakdown condition occurs for operational circuitry. Examples of conventional circuits having a set trigger condition, and typically a set hold condition as well, include diode-triggered SCRs (DTSCRs). Once set, however, adjusting (e.g. changing, altering, etc.) the trigger condition, often requires redesign of the protection circuit. That is, the protection circuits are typically “hard-wired” and are not modified after the integrated circuit is fabricated. Also, trigger conditions for ESD protection and protection against latch-up conditions are often different, thus, having a protection circuit with a trigger condition set to protect against one condition may be a compromise for protecting against the other over-limit electrical conditions. Moreover, adding a dedicated ESD circuit may increase the capacitance seen at the input or output node, which may be unacceptable in high-speed I/O circuits. In addition to exhibiting low capacitance, adequate protection circuits for high-speed applications may in some cases need to be able to dissipate high levels of current, switch on with fast transient response times, and not cause undesirable latch-up.